The present invention generally relates to the field of decoders, and particularly to a decoder with a single critical path for a very high speed synchronous memory.
A series of AND gates or a series of NOR gates, which are the complement of AND gates, are used for decoding of logical input signals, to address memory matrices. As an example, for each group of AND circuits, hereinafter called AND blocks or conventional decoders, there is provided a plurality of logical input signals, depending on the operation to be performed, and there is one output decoded line for each conventional decoder. Associated with each conventional decoder is also a clock pulse input to provide the necessary switching logic for the proper operation of the devices. The conventional decoder blocks are commonly used in the MOSFET large scale integration technology to provide addressing or accessing signals for storage memory arrays. The number of address lines for the memory has been limited by the number of decoded output lines available from the conventional decoders for a particular chip size wherein the spacing between the decoded output lines is referred to as xe2x80x9cpitchxe2x80x9d. Consequently, using MOSFET technology ground rules suitable for maximum density memory fabrication put a restriction on the minimum pitch and minimum array dimensions achievable with these ground rules using conventional decoders, the limitation being the minimum pitch dimension of the conventional decoders.
When a word line decodes an address, the decoder is usually drawn as a NAND gate. This NAND gate takes a large layout area in the tight row decoder pitch. To drive these arrayed NAND gates, the pre-decoder output driver is big.
If a dynamic NAND gate is used for a decoder, a pre-charger signal is required to disable the word line and this pre-charger driver size will be big. A big driver size makes a big load on the previous stage and it makes lower performance also. And it may cause skew or race problem of address and control signal.
An object of the present invention is to provide word line decoder and driver circuits for high density semiconductor memories.
Accordingly, the present invention is directed to a decoder scheme in which one row address (usually the lowest significant bit address) is controlled to be a critical path by address set up control and word line disable timing. Pre-decoded address with the above address bit will control the PMOS transistors of the pseudo AND or pseudo NAND gate.
This invention is smaller and faster than a full AND or full NAND implementation and simpler than a dynamic AND or dynamic NAND implementation as it relates to the control signal derivation.
This invention presents a decoder comprising a first stage circuit having two or more first inputs which generates one or more first outputs; and a second stage circuit having at least one second input and at least one second output, wherein the one or more first outputs supplies a signal to the at least one second input, wherein at least one of the group consisting of the first stage circuit and the second stage circuit includes either a pseudo AND gate or a pseudo NAND gate.
This invention presents a method of decoding, comprising the steps of generating a signal responsive to two or more address bits and enabling a decoder by the generated signal.
It is to be understood that both the forgoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.